Z8 Encore!® Motor Control Flash MCUs
Product Specification
172
If the slave does not acknowledge the address byte, the I2C controller sets the NCKI
bit in the I2C Status Register, sets the ACKVbit, and clears the ACKbit in the I2C State
Register. The software responds to the Not Acknowledge interrupt by setting the STOP
bit and clearing the TXIbit. The I2C controller flushes the Transmit Data Register,
sends a STOPcondition on the bus, and clears the STOPand NCKIbits. The transaction
is complete, and the following steps can be ignored.
12. The I2C controller loads the contents of the I2C Shift Register with the contents of the
I2C Data Register.
13. The I2C controller shifts the data out via the SDA signal. After the first bit is sent, the
transmit interrupt asserts.
14. If more bytes remain to be sent, return to Step 9.
15. When there is no more data to be sent, the software responds by setting the STOPbit of
the I2C Control Register (or the STARTbit to initiate a new transaction).
16. If no additional transaction is queued by the master, the software can clear the TXIbit
of the I2C Control Register.
17. The I2C controller completes transmission of the data on the SDA signal.
18. The I2C controller sends a STOPcondition to the I2C bus.
If the slave terminates the transaction early by responding with a Not Acknowledge during
the transfer, the I2C controller asserts the NCKIinterrupt and halts. The software must ter-
minate the transaction by setting either the STOPbit (end transaction) or the STARTbit
(end this transaction, start a new one). In this case, it is not necessary for software to set
the FLUSHbit of the I2CCTL Register to flush the data that was previously written but not
transmitted. The I2C controller hardware automatically flushes transmit data in this not
acknowledge case.
Note:
Master Write Transaction with a 10-Bit Address
Figure 29 illustrates the data transfer format from a master to a 10-bit addressed slave.
S
Slave Address
1st Byte
W=0
A
Slave Address
2nd Byte
A
Data
A
Data
A/A
F/S
Figure 29. Data Transfer Format—Master Write Transaction with a 10-Bit Address
The first seven bits transmitted in the first byte are 11110XX. The two XXbits are the two
most significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
Read/Write control bit (which is cleared to 0). The transmit operation is performed in the
same manner as 7-bit addressing.
The procedure for a master transmit operation to a 10-bit addressed slave is as follows:
I2C Master/Slave Controller
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
