Z8FMC16100 Series Flash MCU
Product Specification
177
17. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister (the third address transfer).
18. The I2C controller sends 11110b, followed by the two most-significant bits of the
slave read address and a 1 (Read).
19. The I2C slave sends an Acknowledge by pulling the SDA signal Low during the next
High period of SCL.
20. The I2C controller shifts in a byte of data from the slave.
21. The I2C controller asserts the Receive interrupt.
22. The software responds by reading the I2C Data Register. If the next data byte is to be
the final byte, the software must set the NAKbit of the I2C Control Register.
23. The I2C controller sends an Acknowledge or Not Acknowledge to the I2C slave, based
on the value of the NAKbit.
24. If there are more bytes to transfer, the I2C controller returns to Step 18.
25. The I2C controller generates a NAK interrupt (the NCKIbit in the I2CISTAT Regis-
ter).
26. The software responds by setting the STOPbit of the I2C Control Register.
27. A STOPcondition is sent to the I2C slave.
Slave Transactions
The following sections describe Read and Write transactions to the I2C controller config-
ured for 7- and 10-bit slave modes.
Slave Address Recognition
The following slave address recognition options are supported.
Slave 7-Bit Address Recognition Mode. If IRM= 0 during the address phase and the
controller is configured for MASTER/SLAVE or SLAVE 7-bit address mode, the hard-
ware detects a match to the 7-bit slave address defined in the I2CSLVAD Register and
generates the slave address match interrupt (theSAMbit = 1 in the I2CISTAT Register).
The I2C controller automatically responds during the Acknowledge phase with the value
in the NAKbit of the I2CCTL Register.
Slave 10-Bit Address Recognition Mode. If IRM= 0 during the address phase and the
controller is configured for MASTER/SLAVE or SLAVE 10-bit address mode, the hard-
ware detects a match to the 10-bit slave address defined in the I2CMODE and I2CSLVAD
registers and generates the slave address match interrupt (the SAMbit = 1 in the I2CISTAT
Register). The I2C controller automatically responds during the Acknowledge phase with
the value in the NAKbit of the I2CCTL Register.
PS024604-1005
P R E L I M I N A R Y
Slave Transactions
ZILOG [ ZILOG, INC. ]
