Z8 Encore!® Motor Control Flash MCUs
Product Specification
178
General Call and Start Byte Address Recognition. If GCE= 1 and IRM= 0 during the
address phase, and the controller is configured for MASTER/SLAVE or SLAVE in either
7- or 10-bit address modes, the hardware detects a match to the General Call Address or
the START byte and generates the slave address match interrupt. A General Call Address
is a 7-bit address of all 0’s with the R/W bit = 0. A START byte is a 7-bit address of all 0’s
with the R/W bit = 1. The SAMand GCAbits are set in the I2CISTAT Register. The RDbit in
the I2CISTAT Register distinguishes a General Call Address from a START byte which is
cleared to 0 for a General Call Address). For a General Call Address, the I2C controller
automatically responds during the address acknowledge phase with the value in the NAK
bit of the I2CCTL Register. If the software is set to process the data bytes associated with
the GCAbit, the IRMbit can optionally be set following the SAMinterrupt to allow the soft-
ware to examine each received data byte before deciding to set or clear the NAKbit.
A START byte will not be acknowledged—a requirement of the I2C specification.
Software Address Recognition. To disable hardware address recognition, the IRMbit
must be set to 1 prior to the reception of the address byte(s). When IRM= 1, each received
byte generates a receive interrupt (RDRF= 1 in the I2CISTAT Register). The software must
examine each byte and determine whether to set or clear the NAKbit. The slave holds SCL
Low during the Acknowledge phase until the software responds by writing to the I2CCTL
Register. The value written to the NAKbit is used by the controller to drive the I2C bus,
then releasing the SCL. The SAM and GCAbits are not set when IRM= 1 during the address
phase, but the RDbit is updated based on the first address byte.
Slave Transaction Diagrams
In the following transaction diagrams, the shaded regions indicate data transferred from
the master to the slave, and the unshaded regions indicate the data transferred from the
slave to the master. The transaction field labels are defined as follows:
S
W
A
A
P
Start
Write
Acknowledge
Not Acknowledge
Stop
Slave Receive Transaction with 7-Bit Address
The data transfer format for writing data from a master to a slave in 7-bit address mode is
shown in Figure 32. The procedure that follows describes the I2C Master/Slave Controller
operating as a slave in 7-bit addressing mode and receiving data from the bus master.
I2C Master/Slave Controller
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
