Z8FMC16100 Series Flash MCU
Product Specification
173
1. The software initializes the MODEfield in the I2C Mode Register for MASTER/
SLAVE mode with 7- or 10-bit addressing (the I2C bus protocol allows the mixing of
slave address types). The MODEfield selects the address width for this mode when
addressed as a slave (but not for the remote slave). The software asserts the IENbit in
the I2C Control Register.
2. The software asserts the TXIbit of the I2C Control Register to enable transmit inter-
rupts.
3. The I2C interrupt asserts because the I2C Data Register is empty.
4. The software responds to the TDREinterrupt by writing the first slave address byte
(11110xx0). The least-significant bit must be 0 for the write operation.
5. The software asserts the STARTbit of the I2C Control Register.
6. The I2C controller sends a STARTcondition to the I2C slave.
7. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister.
8. After one bit of the address is shifted out by the SDA signal, the transmit interrupt
asserts.
9. The software responds by writing the second byte of address into the contents of the
I2C Data Register.
10. The I2C controller shifts the remainder of the first byte of the address and the Write bit
out via the SDA signal.
11. The I2C slave sends an Acknowledge by pulling the SDA signal Low during the next
high period of SCL. The I2C controller sets the ACKbit in the I2C Status Register.
If the slave does not acknowledge the first address byte, the I2C controller sets the
NCKIbit in the I2C Status Register, sets the ACKVbit, and clears the ACKbit in the I2C
State Register. The software responds to the Not Acknowledge interrupt by setting the
STOPbit and clearing the TXIbit. The I2C controller flushes the second address byte
from the data register, sends a STOPcondition on the bus, and clears the STOPand
NCKIbits. The transaction is complete, and the following steps can be ignored.
12. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister (2nd address byte).
13. The I2C controller shifts the second address byte out via the SDA signal. After the
first bit has been sent, the transmit interrupt asserts.
14. The software responds by writing the data to be written out to the I2C Control Regis-
ter.
15. The I2C controller shifts out the remainder of the second byte of the slave address (or
ensuing data bytes, if looping) via the SDA signal.
PS024604-1005
P R E L I M I N A R Y
Master Transactions
ZILOG [ ZILOG, INC. ]
