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Z8FMC04100QKSG 参数 Datasheet PDF下载

Z8FMC04100QKSG图片预览
型号: Z8FMC04100QKSG
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采-R电机控制闪存MCU [Z8 Encore-R Motor Control Flash MCUs]
分类和应用: 闪存微控制器和处理器外围集成电路电机时钟
文件页数/大小: 402 页 / 4558 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8FMC16100 Series Flash MCU  
Product Specification  
155  
Slave Operation  
The SPI block is configured for SLAVE mode operation by setting the SPIEN bit to 1 and  
the MMEN bit to 0 in the SPICTL Register and setting the SSIO bit to 0 in the SPIMODE  
Register. The IRQE, PHASE, CLKPOL, and WORbits in the SPICTL Register and the NUM-  
BITSfield in the SPIMODE Register must be set to be consistent with the other SPI  
devices. The STR bit in the SPICTL Register can be used, if appropriate, to force a start-  
up interrupt. The BIRQbit in the SPICTL Register and the SSVbit in the SPIMODE Reg-  
ister are not used in SLAVE mode. The SPI baud rate generator is not used in SLAVE  
mode; therefore, the SPIBRH and SPIBRL registers do not require initialization.  
If the slave contains data to send to the master, the data should be written to the SPIDAT  
Register before the transaction starts (first edge of SCK when SS is asserted). If the SPI-  
DAT Register is not written prior to the slave transaction, the MISO pin outputs the value  
that is currently in the SPIDAT Register.  
Due to the delay resulting from synchronization of the SPI input signals to the internal sys-  
tem clock, the maximum SPICLK baud rate that can be supported in SLAVE mode is the  
system clock frequency (XIN) divided by 8. This rate is controlled by the SPI master.  
Error Detection  
The SPI contains error detection logic that supports SPI communication protocols and rec-  
ognizes when communication errors have occurred. The SPI Status Register indicates  
when a data transmission error has been detected.  
Overrun  
An overrun error (write collision) indicates that a Write to the SPI Data Register was  
attempted while a data transfer is in progress (in either MASTER or SLAVE modes). An  
overrun sets the OVRbit in the SPI Status Register to 1. Writing a 1 to OVR clears this  
error flag. The SPI Data Register is not altered when a Write occurs while a data transfer is  
in progress.  
Mode Fault  
A mode fault indicates when more than one master is trying to communicate at the same  
time (a multimaster collision). The mode fault is detected when the enabled master’s SS  
pin is asserted. A mode fault sets the COLbit in the SPI Status Register to 1. Writing a 1 to  
COLclears this error flag.  
Slave Mode Abort  
In SLAVE mode, if the SS pin deasserts before all bits in a character have been trans-  
ferred, the transaction aborts. When this condition occurs, the ABTbit is set in the  
SPISTAT Register as well as the IRQbit (which indicates that the transaction is complete).  
PS024604-1005  
P R E L I M I N A R Y  
Slave Operation