Z8 Encore!® Motor Control Flash MCUs
Product Specification
154
Transfer Format Phase Equals One
Figure 26 illustrates the timing diagram for an SPI transfer in which PHASEis 1. Two
waveforms are depicted for SCK, one for CLKPOLreset to 0, and another for CLKPOLset
to 1.
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4 Bit 3
Bit 4 Bit 3
Bit 2
Bit 2
Bit 1 Bit 0
Bit 1 Bit 0
MISO
Input Sample Time
SS
Figure 26. SPI Timing When Phase is 1
Multimaster Operation
In a multimaster SPI system, all SCK pins are tied together, all MOSI pins are tied
together, and all MISO pins are tied together. All SPI pins must then be configured in
OPEN-DRAIN mode to prevent bus contention. At any time, only one SPI device is con-
figured as the master and all other SPI devices on the bus are configured as slaves. The
master enables a single slave by asserting the SS pin on that slave only. Then, the single
master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the slaves
(including those which are not enabled). The enabled slave drives data out its MISO pin to
the MISO master pin.
For a master device operating in a multimaster system, if the SS pin is configured as an
input and is driven Low by another master, the COLbit is set to 1 in the SPI Status Regis-
ter. The COLbit indicates the occurrence of a multimaster collision (mode fault error con-
dition).
Serial Peripheral Interface
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
