Z8FMC16100 Series Flash MCU
Product Specification
153
Table 83. SPI Clock Phase and Clock Polarity Operation
SCK Transmit
Edge
SCK Receive
Edge
SCK Idle
State
PHASE
CLKPOL
0
0
1
1
0
1
0
1
Falling
Rising
Rising
Falling
Rising
Falling
Falling
Rising
Low
High
Low
High
Transfer Format Phase Equals Zero
Figure 25 illustrates the timing diagram for an SPI transfer in which PHASEis cleared to 0.
The two SCK waveforms show polarity with CLKPOLreset to 0 and with CLKPOLset to
1. The diagram can be interpreted as either a master or slave timing diagram because the
SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly con-
nected between the master and the slave.
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4 Bit 3
Bit 4 Bit 3
Bit 2
Bit 2
Bit 1 Bit 0
Bit 1 Bit 0
MISO
Input Sample Time
SS
Figure 25. SPI Timing When Phase is 0
PS024604-1005
P R E L I M I N A R Y
SPI Clock Phase and Polarity Control
ZILOG [ ZILOG, INC. ]
