Z8FMC16100 Series Flash MCU
Product Specification
151
Operation
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire
interface (serial clock, transmit, receive, and slave select). The SPI block consists of a
transmit/receive shift register, a Baud Rate (clock) Generator, and a control unit.
During an SPI transfer, data is sent and received simultaneously by both the master and the
slave SPI devices. Separate signals are required for data and the serial clock. When an SPI
transfer occurs, a multibit (typically 8-bit) character is shifted out one data pin and an
multibit character is simultaneously shifted in on a second data pin. An 8-bit shift register
in the master and another 8-bit shift register in the slave are connected as a circular buffer.
The SPI shift register is single-buffered in the transmit and receive directions. New data to
be transmitted cannot be written into the shift register until the previous transmission is
complete and receive data (if valid) has been read.
SPI Signals
The four basic SPI signals are:
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•
•
•
Master-In, Slave-Out (MISO)
Master-Out, Slave-In (MOSI)
Serial Clock (SCK)
Slave Select (SS)
The following paragraphs discuss these SPI signals. Each signal is described in both
MASTER and SLAVE modes.
Master-In, Slave-Out
The Master-In, Slave-Out (MISO) pin is configured as an input in a master device and as
an output in a slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. The MISO pin of a slave device is placed in a high-impedance
state if the slave is not selected. When the SPI is not enabled, this signal is in a high-
impedance state.
Master-Out, Slave-In
The Master-Out, Slave-In (MOSI) pin is configured as an output in a master device and as
an input in a slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance
state.
PS024604-1005
P R E L I M I N A R Y
Operation
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