Z8FMC16100 Series Flash MCU
Product Specification
157
SPI Data Register
The SPI Data Register stores both the outgoing (transmit) data and the incoming (receive)
data. Reads from the SPI Data Register always return the current contents of the 8-bit shift
register. Data is shifted out starting with bit 7. The last bit received resides in bit position 0.
With the SPI configured as a master, writing a data byte to this register initiates data trans-
mission. With the SPI configured as a slave, writing a data byte to this register loads the
shift register in preparation for the next data transfer with the external master. In either
MASTER or SLAVE mode, if a transmission is already in progress, Writes to this register
are ignored and the overrun error flag, OVR, is set in the SPI Status Register.
When character length is less than 8 bits (as set by the NUMBITSfield in the SPI Mode Reg-
ister), the transmit character must be left-justified in the SPI Data Register. A received char-
acter of less than 8 bits is right-justified (the final bit received is in bit position 0). For
example, if the SPI is configured for 4-bit characters, the transmit characters must be written
to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0]. See Table 84.
Table 84. SPI Data Register (SPIDATA)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DATA
X
R/W
F60H
ADDR
DATA—Data
Transmit and/or receive data.
PS024604-1005
P R E L I M I N A R Y
SPI Data Register
ZILOG [ ZILOG, INC. ]
