Z8FMC16100 Series Flash MCU
Product Specification
159
SPIEN—SPI Enable
0 = SPI disabled.
1 = SPI enabled.
SPI Status Register
The SPI Status Register indicates the current state of the SPI. All bits revert to their reset
state if the SPIEN bit in the SPICTL Register = 0.
Table 86. SPI Status Register (SPISTAT)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
IRQ
OVR
COL
ABT
Reserved
TXST
SLAS
0
0
0
0
0
0
0
1
R/W*
R
F62H
ADDR
R/W* = Read access. Write a 1 to clear the bit to 0.
IRQ—Interrupt Request
If SPIEN = 1, this bit is set if the STR bit in the SPICTL register is set, or upon completion
of an SPI master or slave transaction. This bit does not set if SPIEN = 0 and the SPI Baud
Rate Generator is used as a timer to generate the SPI interrupt.
0 = No SPI interrupt request pending.
1 = SPI interrupt request is pending.
OVR—Overrun
0 = An overrun error has not occurred.
1 = An overrun error has been detected.
COL—Collision
0 = A multi-master collision (mode fault) has not occurred.
1 = A multi-master collision (mode fault) has been detected.
ABT—SLAVE mode transaction abort
This bit is set if the SPI is configured in SLAVE mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the SPIMODE register. The IRQ bit also sets, indicating the transaction has com-
pleted.
0 = A SLAVE mode transaction abort has not occurred.
1 = A SLAVE mode transaction abort has been detected.
Reserved—Must be 0.
PS024604-1005
P R E L I M I N A R Y
SPI Status Register
ZILOG [ ZILOG, INC. ]
