Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
118
I2C Control Register Definitions
I2C Data Register
The I2C Data register holds the data that is to be loaded into the I2C Shift register during a
write to a slave. This register also holds data that is loaded from the I2C Shift register dur-
ing a read from a slave. The I2C Shift is not accessible in the Register File address space,
but is used only to buffer incoming and outgoing data.
Table 66. I2C Data Register (I2CDATA)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DATA
F50H
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
I2C Status Register
The Read-only I2C Status register indicates the status of the I2C Controller.
Table 67. I2C Status Register (I2CSTAT)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TDRE
RDRF
ACK
10B
RD
TAS
DSS
NCKI
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
F51H
ADDR
TDRE—Transmit Data Register Empty
When the I2C Controller is enabled, this bit is 1 when the I2C Data register is empty.
When active, this bit causes the I2C Controller to generate an interrupt, except when the
I2C Controller is shifting in data during the reception of a byte or when shifting an address
and the RDbit is set. This bit and the interrupt are cleared by writing to the I2CD register.
RDRF—Receive Data Register Full
This bit is set active high when the I2C Controller is enabled and the I2C Controller has
PS017609-0803
I2C Controller
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