Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
119
received a byte of data. When active, this bit causes the I2C Controller to generate an
interrupt. This bit is cleared by reading the I2C Data register.
ACK—Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received.
When set, this bit indicates that an Acknowledge was received for the last byte transmitted
or received.
10B—10-Bit Address
This bit indicates whether a 10- or 7-bit address is being transmitted. After the STARTbit
is set, if the five most-significant bits of the address are 11110B, this bit is set. When set,
it is reset once the first byte of the address has been sent.
RD—Read
This bit indicates the direction of transfer of the data. It is active high during a read. The
status of this bit is determined by the least-significant bit of the I2C Shift register after the
STARTbit is set.
TAS—Transmit Address State
This bit is active high while the address is being shifted out of the I2C Shift register.
DSS—Data Shift State
This bit is active high while data is being transmitted to or from the I2C Shift register.
NCKI—NACK Interrupt
This bit is set high when a Not Acknowledge condition is received or sent and neither the
START nor the STOP bit is active. When set, this bit generates an interrupt that can only
be cleared by setting the STARTor STOPbit, allowing the user to specify whether he
wants to perform a STOPor a repeated START.
I2C Control Register
The I2C Control register enables the I2C operation.
Table 68. I2C Control Register (I2CCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
IEN
START
STOP
BIRQ
TXI
NAK
FLUSH
FILTEN
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F52H
ADDR
IEN—I2C Enable
This bit enables the I2C transmitter and receiver.
PS017609-0803
I2C Controller
ZILOG [ ZILOG, INC. ]
