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Z8F2401VN020SC 参数 Datasheet PDF下载

Z8F2401VN020SC图片预览
型号: Z8F2401VN020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采微控制器与闪存和10位A / D转换器 [Z8 Encore Microcontrollers with Flash Memory and 10-Bit A/D Converter]
分类和应用: 转换器闪存微控制器
文件页数/大小: 246 页 / 1767 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x  
Z8 Encore!®  
114  
14. Software responds by setting the STOPbit of the I2C Control register.  
15. If no new data is to be sent or address is to be sent, software responds by clearing the  
TXIbit of the I2C Control register.  
16. The I2C Controller completes transmission of the data on the SDA signal.  
17. The I2C Controller sends the STOP condition to the I2C bus.  
Writing a Transaction with a 10-Bit Address  
1. The I2C Controller shifts the I2C Shift register out onto SDA signal.  
2. The I2C Controller waits for the slave to send an Acknowledge (by pulling the SDA  
signal Low). If the slave pulls the SDA signal High (Not-Acknowledge), the I2C  
Controller sends a Stop signal.  
3. If the slave needs to service an interrupt, it pulls the SCL signal low, which halts I2C  
operation.  
4. If there is no other data in the I2C Data register or the STOPbit in the I2C Control  
register is set by software, then the Stop signal is sent.  
The data transfer format for a 10-bit addressed slave is illustrated in the figure below.  
Shaded regions indicate data transferred from the I2C Controller to slaves and unshaded  
regions indicate data transferred from the slaves to the I2C Controller.  
Slave Address  
2nd Byte  
Slave Address  
1st 7 bits  
A
W=0  
S
A
Data  
A
Data  
A/A P  
Figure 80. 10-Bit Addressed Slave Data Transfer Format  
The first seven bits transmitted in the first byte are 11110XX. The two bits XXare the two  
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the  
write signal. The transmit operation is carried out in the same manner as 7-bit addressing.  
The data transfer format for a transmit operation on a 10-bit addressed slave is as follows:  
1. Software asserts the IENbit in the I2C Control register.  
2. Software asserts the TXIbit of the I2C Control register to enable Transmit interrupts.  
3. The I2C interrupt asserts because the I2C Data register is empty.  
4. Software responds to the TDREbit by writing the first slave address byte. The least-  
significant bit must be 0 for the write operation.  
5. Software asserts the START bit of the I2C Control register.  
6. The I2C Controller sends the START condition to the I2C slave.  
PS017609-0803  
I2C Controller