Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
120
START—Send Start Condition
This bit sends the Start condition. Once asserted, it is cleared by the I2C Controller after it
sends the START condition or by deasserting the IENbit. After this bit is set, the Start
condition is sent if there is data in the I2C Data or I2C Shift register. If there is no data in
one of these registers, the I2C Controller waits until data is loaded. If this bit is set while
the I2C Controller is shifting out data, it generates a START condition after the byte shifts
and the acknowledge phase completed. If the STOPbit is also set, it also waits until the
STOP condition is sent before the START condition. If this bit is 1, it cannot be cleared to
0 by writing to the register.This bit clears when the I2C is disabled.
STOP—Send Stop Condition
This bit causes the I2C Controller to issue a Stop condition after the byte in the I2C Shift
register has completed transmission or after a byte has been received in a receive opera-
tion. Once set, this bit is reset by the I2C Controller after a Stop condition has been sent or
by deasserting the IENbit. If this bit is 1, it cannot be cleared to 0 by writing to the regis-
ter.This bit clears when the I2C is disabled.
BIRQ—Baud Rate Generator Interrupt Request
This bit causes an interrupt to occur every time the baud rate generator counts down to
zero. This bit allows the I2C Controller to be used as an additional counter when it is not
being used elsewhere. This bit must only be set when the I2C Controller is disabled.
TXI—Enable TDRE interrupts
This bit enables interrupts when the I2C Data register is empty on the I2C Controller.
NAK—Send NAK
This bit sends a Not Acknowledge condition after the next byte of data has been read from
the I2C slave. Once asserted, it is deasserted after a Not Acknowledge is sent or the IEN
bit is deasserted.
FLUSH—Flush Data
Setting this bit to 1 clears the I2C Data register and sets the TDRE bit to 1. This bit allows
flushing of the I2C Data register when an NAK is received after the data has been sent to
the I2C Data register. Reading this bit always returns 0.
FILTEN—I2C Signal Filter Enable
Setting this bit to 1 enables low-pass digital filters on the SDA and SCL input signals.
These filters reject any input pulse with periods less than a full system clock cycle. The fil-
ters introduce a 3-system clock cycle latency on the inputs.
PS017609-0803
I2C Controller
ZILOG [ ZILOG, INC. ]
