Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
106
1. Disable the SPI by clearing the SPIENbit in the SPI Control register to 0.
2. Load the desired 16-bit count value into the SPI Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BIRQbit in the SPI Control register to 1.
SPI Control Register Definitions
SPI Data Register
The SPI Data register stores both the outgoing (transmit) data and the incoming (received)
data. Reads from the SPI Data register always return the current contents of the 8-bit shift
register.
With the SPI configured as a Master, writing a data byte to this register initiates the data
transmission. With the SPI configured as a Slave, writing a data byte to this register loads
the shift register in preparation for the next data transfer with the external Master. In either
the Master or Slave modes, if a transmission is already in progress, writes to this register
are ignored and the Overrun error flag, OVR, is set in the SPI Status register.
When the character length is less than 8 bits (as set by the NUMBITSfield in the SPI Mode
register), the transmit character must be left justified in the SPI Data register. A received
character of less than 8 bits will be right justified. For example, if the SPI is configured for
4-bit characters, the transmit characters must be written to SPIDATA[7:4] and the received
characters are read from SPIDATA[3:0].
Table 60. SPI Data Register (SPIDATA)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DATA
F60H
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
DATA—Data
Transmit and/or receive data.
PS017610-0404
Serial Peripheral Interface
ZILOG [ ZILOG, INC. ]
