Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
108
SPIEN—SPI Enable
0 = SPI disabled.
1 = SPI enabled.
SPI Status Register
The SPI Status register indicates the current state of the SPI.
Table 62. SPI Status Register (SPISTAT)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
IRQ
OVR
COL
Reserved
TXST
SLAS
0
0
0
0
0
1
R/W*
R/W*
R/W*
R
R
R
F62H
ADDR
R/W* = Read access. Write a 1 to clear the bit to 0.
IRQ—Interrupt Request
0 = No SPI interrupt request pending.
1 = SPI interrupt request is pending.
OVR—Overrun
0 = An overrun error has not occurred.
1 = An overrun error has been detected.
COL—Collision
0 = A multi-master collision (mode fault) has not occurred.
1 = A multi-master collision (mode fault) has been detected.
Reserved
These bits are reserved and must be 0.
TXST—Transmit Status
0 = No data transmission currently in progress.
1 = Data transmission currently in progress.
SLAS—Slave Select
If SPI enabled as a Slave,
0 = SS input pin is asserted (Low)
1 = SS input is not asserted (High).
If SPI enabled as a Master, this bit is not applicable.
PS017610-0404
Serial Peripheral Interface
ZILOG [ ZILOG, INC. ]
