Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
109
SPI Mode Register
The SPI Mode register configures the character bit width and the direction and value of the
SS pin.
Table 63. SPI Mode Register (SPIMODE)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
Reserved
NUMBITS[2:0]
SSIO
SSV
0
0
0
R/W
0
0
0
R
R/W
R/W
R/W
R/W
F63H
ADDR
Reserved
These bits are reserved and must be 0.
NUMBITS[2:0]—Number of Data Bits Per Character to Transfer
This field contains the number of bits to shift for each character transfer. Refer to the SPI
Data Register description for information on valid bit positions when the character length
is less than 8-bits.
000 = 8 bits
001 = 1 bit
010 = 2 bits
011 = 3 bits
100 = 4 bits
101 = 5 bits
110 = 6 bits
111 = 7 bits.
SSIO—Slave Select I/O
0 = SS pin configured as an input.
1 = SS pin configured as an output (Master mode only).
SSV—Slave Select Value
If SSIO = 1 and SPI configured as a Master:
0 = SS pin driven Low (0).
1 = SS pin driven High (1).
This bit has no effect if SSIO= 0 or SPI configured as a Slave.
PS017610-0404
Serial Peripheral Interface
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