Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
105
Error Detection
The SPI contains error detection logic to support SPI communication protocols and recog-
nize when communication errors have occurred. The SPI Status register indicates when a
data transmission error has been detected.
Overrun (Write Collision)
An overrun error (write collision) indicates a write to the SPI Data register was attempted
while a data transfer is in progress. An overrun sets the OVRbit in the SPI Status register
to 1. Writing a 1 to OVRclears this error flag.
Mode Fault (Multi-Master Collision)
A mode fault indicates when more than one Master is trying to communicate at the same
time (a multi-master collision). The mode fault is detected when the enabled Master’s SS
pin is asserted. A mode fault sets the COLbit in the SPI Status register to 1. Writing a 1 to
COLclears this error flag.
SPI Interrupts
When SPI interrupts are enabled, the SPI generates an interrupt after data transmission.
The SPI in Master mode generates an interrupt after a character has been sent. A character
can be defined to be 1 through 8 bits by the NUMBITSfield in the SPI Mode register. The
SPI in Slave mode generates an interrupt when the SS signal deasserts to indicate comple-
tion of the data transfer. Writing a 1 to the IRQbit in the SPI Status Register clears the
pending interrupt request. If the SPI is disabled, an SPI interrupt can be generated by a
Baud Rate Generator time-out.
SPI Baud Rate Generator
In SPI Master mode, the Baud Rate Generator creates a lower frequency serial clock
(SCK) for data transmission synchronization between the Master and the external Slave.
The input to the Baud Rate Generator is the system clock. The SPI Baud Rate High and
Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the SPI Baud
Rate Generator. The reload value must be greater than or equal to 0002Hfor SPI operation
(maximum baud rate is system clock frequency divided by 4). The SPI baud rate is calcu-
lated using the following equation:
System Clock Frequency (Hz)
---------------------------------------------------------------------------
SPI Baud Rate (bits/s) =
2 × BRG[15:0]
When the SPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
PS017610-0404
Serial Peripheral Interface
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