Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
103
Transfer Format PHASE Equals Zero
Figure 77 illustrates the timing diagram for an SPI transfer in which PHASEis cleared to
0. The two SCK waveforms show polarity with CLKPOLreset to 0 and with CLKPOLset
to one. The diagram may be interpreted as either a Master or Slave timing diagram since
the SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly
connected between the Master and the Slave.
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7
Bit7
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
MISO
Input Sample Time
SS
Figure 77. SPI Timing When PHASE is 0
Transfer Format PHASE Equals One
Figure 78 illustrates the timing diagram for an SPI transfer in which PHASEis one. Two
waveforms are depicted for SCK, one for CLKPOLreset to 0 and another for CLKPOLset
to 1.
PS017610-0404
Serial Peripheral Interface
ZILOG [ ZILOG, INC. ]
