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Z8F2401VN020SC 参数 Datasheet PDF下载

Z8F2401VN020SC图片预览
型号: Z8F2401VN020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采微控制器与闪存和10位A / D转换器 [Z8 Encore Microcontrollers with Flash Memory and 10-Bit A/D Converter]
分类和应用: 转换器闪存微控制器
文件页数/大小: 246 页 / 1767 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x  
Z8 Encore!®  
104  
SCK  
(CLKPOL = 0)  
SCK  
(CLKPOL = 1)  
MOSI  
Bit7  
Bit7  
Bit6  
Bit6  
Bit5  
Bit5  
Bit4  
Bit4  
Bit3  
Bit3  
Bit2  
Bit2  
Bit1  
Bit1  
Bit0  
Bit0  
MISO  
Input Sample Time  
SS  
Figure 78. SPI Timing When PHASE is 1  
Multi-Master Operation  
In a multi-master SPI system, all SCK pins are tied together, all MOSI pins are tied  
together and all MISO pins are tied together. All SPI pins must then be configured in  
open-drain mode to prevent bus contention. At any one time, only one SPI device is con-  
figured as the Master and all other SPI devices on the bus are configured as Slaves. The  
Master enables a single Slave by asserting the SS pin on that Slave only. Then, the single  
Master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the Slaves  
(including those which are not enabled). The enabled Slave drives data out its MISO pin to  
the MISO Master pin.  
For a Master device operating in a multi-master system, if the SS pin is configured as an  
input and is driven Low by another Master, the COLbit is set to 1 in the SPI Status Regis-  
ter. The COLbit indicates the occurrence of a multi-master collision (mode fault error con-  
dition).  
PS017610-0404  
Serial Peripheral Interface