Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
100
VCC
SPI Master
SS
To Slave #2’s SS Pin
To Slave #1’s SS Pin
From Slave
GPIO
GPIO
8-bit Shift Register
Bit 7
Bit 0
MISO
MOSI
To Slave
To Slave
SCK
Baud Rate
Generator
Figure 75. SPI Configured as a Master in a Single Master, Multiple Slave System
SPI Slave
From Master
SS
8-bit Shift Register
Bit 7 Bit 0
MISO
MOSI
To Master
From Master
SCK
From Master
Figure 76. SPI Configured as a Slave
Operation
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire
interface (serial clock, transmit, receive and Slave select). The SPI block consists of trans-
PS017610-0404
Serial Peripheral Interface
ZILOG [ ZILOG, INC. ]
