Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
50
Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) register (Table 25) stores interrupt requests for both vec-
tored and polled interrupts. When a request is presented to the interrupt controller, the cor-
responding bit in the IRQ2 register becomes 1. If interrupts are globally enabled (vectored
interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts
are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1
register to determine if any interrupt requests are pending.
Table 25. Interrupt Request 2 Register (IRQ2)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
T3I
U1RXI
U1TXI
DMAI
PC3I
PC2I
PC1I
PC0I
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC6H
ADDR
T3I—Timer 3 Interrupt Request
0 = No interrupt request is pending for Timer 3.
1 = An interrupt request from Timer 3 is awaiting service.
U1RXI—UART 1 Receive Interrupt Request
0 = No interrupt request is pending for the UART1 receiver.
1 = An interrupt request from UART1 receiver is awaiting service.
U1TXI—UART 1 Transmit Interrupt Request
0 = No interrupt request is pending for the UART 1 transmitter.
1 = An interrupt request from the UART 1 transmitter is awaiting service.
DMAI—DMA Interrupt Request
0 = No interrupt request is pending for the DMA.
1 = An interrupt request from the DMA is awaiting service.
PCxI—Port C Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
where x indicates the specific GPIO Port C pin number (0 through 3).
PS017610-0404
Interrupt Controller
ZILOG [ ZILOG, INC. ]
