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Z8F1602AR020EC 参数 Datasheet PDF下载

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型号: Z8F1602AR020EC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采微控制器与闪存和10位A / D转换器 [Z8 Encore Microcontrollers with Flash Memory and 10-Bit A/D Converter]
分类和应用: 转换器闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 246 页 / 1767 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x  
Z8 Encore!®  
53  
Table 30. IRQ1 Enable High Bit Register (IRQ1ENH)  
BITS  
FIELD  
RESET  
R/W  
7
6
5
4
3
2
1
0
PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
FC4H  
ADDR  
PADxENH—Port A or Port D Bit[x] Interrupt Request Enable High Bit  
Refer to the Interrupt Port Select register for selection of either Port A or Port D as the  
interrupt source.  
Table 31. IRQ1 Enable Low Bit Register (IRQ1ENL)  
BITS  
FIELD  
RESET  
R/W  
7
6
5
4
3
2
1
0
PAD7ENL PAD6ENL PAD5ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL PAD0ENL  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
FC5H  
ADDR  
PADxENL—Port A or Port D Bit[x] Interrupt Request Enable Low Bit  
Refer to the Interrupt Port Select register for selection of either Port A or Port D as the  
interrupt source.  
IRQ2 Enable High and Low Bit Registers  
The IRQ2 Enable High and Low Bit registers (Tables 33 and 34) form a priority encoded  
enabling for interrupts in the Interrupt Request 2 register. Priority is generated by setting  
bits in each register. Table 32 describes the priority control for IRQ2.  
Table 32. IRQ2 Enable and Priority Encoding  
IRQ2ENH[x] IRQ2ENL[x] Priority  
Description  
Disabled  
Low  
0
0
1
1
0
1
0
1
Disabled  
Level 1  
Level 2  
Level 3  
Nominal  
High  
where x indicates the register bits from 0 through 7.  
PS017610-0404  
Interrupt Controller