Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
51
IRQ0 Enable High and Low Bit Registers
The IRQ0 Enable High and Low Bit registers (Tables 27 and 28) form a priority encoded
enabling for interrupts in the Interrupt Request 0 register. Priority is generated by setting
bits in each register. Table 26 describes the priority control for IRQ0.
Table 26. IRQ0 Enable and Priority Encoding
IRQ0ENH[x] IRQ0ENL[x] Priority
Description
Disabled
Low
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Nominal
High
where x indicates the register bits from 0 through 7.
Table 27. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
T2ENH
T1ENH
T0ENH
U0RENH U0TENH
I2CENH
SPIENH ADCENH
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC1H
ADDR
T2ENH—Timer 2 Interrupt Request Enable High Bit
T1ENH—Timer 1 Interrupt Request Enable High Bit
T0ENH—Timer 0 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
I2CENH—I2C Interrupt Request Enable High Bit
SPIENH—SPI Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
PS017610-0404
Interrupt Controller
ZILOG [ ZILOG, INC. ]
