Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
46
Architecture
Figure 65 illustrates a block diagram of the interrupt controller.
High
Priority
Port Interrupts
Vector
Priority
Mux
IRQ Request
Medium
Priority
Internal Interrupts
Low
Priority
Figure 65. Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
•
•
•
Execution of an EI (Enable Interrupt) instruction
Execution of an IRET (Return from Interrupt) instruction
Writing a 1 to the IRQEbit in the Interrupt Control register
Interrupts are globally disabled by any of the following actions:
•
•
Execution of a DI (Disable Interrupt) instruction
eZ8 CPU acknowledgement of an interrupt service request from the interrupt
controller
•
•
Writing a 0 to the IRQEbit in the Interrupt Control register
Reset
PS017610-0404
Interrupt Controller
ZILOG [ ZILOG, INC. ]
