Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
38
PADDR[7:0]—Port Address
The Port Address selects one of the sub-registers accessible through the Port Control reg-
ister.
PADDR[7:0] Port Control sub-register accessible using the Port A-H Control Registers
00H
01H
No function. Provides some protection against accidental Port reconfiguration.
Data Direction
02H
Alternate Function
03H
Output Control (Open-Drain)
High Drive Enable
04H
05H
Stop Mode Recovery Source Enable.
No function.
06H-FFH
Port A-H Control Registers
The Port A-H Control registers set the GPIO port operation. The value in the correspond-
ing Port A-H Address register determines the control sub-registers accessible using the
Port A-H Control register (Table 14).
Table 14. Port A-H Control Registers (PxCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PCTL
00H
R/W
FD1H, FD5H, FD9H, FDDH, FE1H, FE5H, FE9H, FEDH
ADDR
PCTL[7:0]—Port Control
The Port Control register provides access to all sub-registers that configure the GPIO Port
operation.
PS017610-0404
General-Purpose I/O
ZILOG [ ZILOG, INC. ]
