Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
34
Table 10. Port Availability by Device and Package Type (Continued)
Device
Packages
44-pin
Port A Port B Port C Port D Port E Port F Port G Port H
Z8F6401
Z8F6402
Z8F6403
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[6:0]
[7:0]
[7:0]
-
-
-
-
64- and 68-pin
80-pin
[7:0]
[7:0]
[7]
[3]
[3:0]
[3:0]
[7:0]
[7:0]
Architecture
Figure 64 illustrates a simplified block diagram of a GPIO port pin. In this figure, the abil-
ity to accommodate alternate functions and variable port current drive strength are not
illustrated.
Port Input
Data Register
Schmitt Trigger
Q
D
Q
D
System
Clock
VDD
Port Output Control
Port Output
Data Register
DATA
Bus
D
Q
Port
Pin
System
Clock
Port Data Direction
GND
Figure 64. GPIO Port Pin Block Diagram
GPIO Alternate Functions
Many of the GPIO port pins can be used as both general-purpose I/O and to provide access
to on-chip peripheral functions such as the timers and serial communication devices. The
Port A-H Alternate Function sub-registers configure these pins for either general-purpose
I/O or alternate function operation. When a pin is configured for alternate function, control
PS017610-0404
General-Purpose I/O