Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
37
Table 12. GPIO Port Registers and Sub-Registers
Port Register Mnemonic
Port Register Name
PxADDR
Port A-H Address Register
(Selects sub-registers)
PxCTL
Port A-H Control Register
(Provides access to sub-registers)
PxIN
Port A-H Input Data Register
Port A-H Output Data Register
PxOUT
Port Sub-Register Mnemonic Port Register Name
PxDD
PxAF
Data Direction
Alternate Function
Output Control (Open-Drain)
High Drive Enable
PxOC
PxHDE
PxSMRE
STOP Mode Recovery Source
Enable
Port A-H Address Registers
The Port A-H Address registers select the GPIO Port functionality accessible through the
Port A-H Control registers. The Port A-H Address and Control registers combine to pro-
vide access to all GPIO Port control (Table 13).
Table 13. Port A-H GPIO Address Registers (PxADDR)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PADDR[7:0]
00H
R/W
FD0H, FD4H, FD8H, FDCH, FE0H, FE4H, FE8H, FECH
ADDR
PS017610-0404
General-Purpose I/O
ZILOG [ ZILOG, INC. ]
