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Z8F082ASH020SC 参数 Datasheet PDF下载

Z8F082ASH020SC图片预览
型号: Z8F082ASH020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采XP -R F08xA系列与扩展外设 [Z8 Encore XP-R F08xA Series with eXtended Peripherals]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 244 页 / 2750 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore! XP® F08xA Series  
Product Specification  
51  
Table 32. Interrupt Request 0 Register (IRQ0)  
BITS  
7
6
5
4
3
2
1
0
Reserved  
T1I  
T0I  
U0RXI  
U0TXI  
Reserved Reserved  
ADCI  
FIELD  
RESET  
R/W  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
FC0H  
ADDR  
Reserved—Must be 0.  
T1I—Timer 1 Interrupt Request  
0 = No interrupt request is pending for Timer 1.  
1 = An interrupt request from Timer 1 is awaiting service.  
T0I—Timer 0 Interrupt Request  
0 = No interrupt request is pending for Timer 0.  
1 = An interrupt request from Timer 0 is awaiting service.  
U0RXI—UART 0 Receiver Interrupt Request  
0 = No interrupt request is pending for the UART 0 receiver.  
1 = An interrupt request from the UART 0 receiver is awaiting service.  
U0TXI—UART 0 Transmitter Interrupt Request  
0 = No interrupt request is pending for the UART 0 transmitter.  
1 = An interrupt request from the UART 0 transmitter is awaiting service.  
ADCI—ADC Interrupt Request  
0 = No interrupt request is pending for the Analog-to-Digital Converter.  
1 = An interrupt request from the Analog-to-Digital Converter is awaiting service.  
Interrupt Request 1 Register  
The Interrupt Request 1 (IRQ1) register (Table 33) stores interrupt requests for both vec-  
tored and polled interrupts. When a request is presented to the interrupt controller, the cor-  
responding bit in the IRQ1 register becomes 1. If interrupts are globally enabled (vectored  
interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts  
are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1  
register to determine if any interrupt requests are pending.  
PS024705-0405  
P R E L I M I N A R Y  
Interrupt Controller