Z8 Encore! XP® F08xA Series
Product Specification
48
Table 31. Trap and Interrupt Vectors in Order of Priority (Continued)
Program Memory
Priority Vector Address
Lowest 0036H
0038H
Interrupt or Trap Source
Port C0, both input edges
Reserved
Architecture
Figure 7 illustrates the interrupt controller block diagram.
High
Port Interrupts
Priority
Vector
Priority
Mux
IRQ Request
Medium
Priority
Internal Interrupts
Low
Priority
Figure 7.Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
•
•
Execution of an EI (Enable Interrupt) instruction
Execution of an IRET (Return from Interrupt) instruction
PS024705-0405
P R E L I M I N A R Y
Interrupt Controller
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