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Z8F082ASH020SC 参数 Datasheet PDF下载

Z8F082ASH020SC图片预览
型号: Z8F082ASH020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采XP -R F08xA系列与扩展外设 [Z8 Encore XP-R F08xA Series with eXtended Peripherals]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 244 页 / 2750 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore! XP® F08xA Series  
Product Specification  
50  
To avoid missing interrupts, use the following coding style to clear bits in  
the Interrupt Request 0 register:  
Caution:  
Good coding style that avoids lost interrupt requests:  
ANDX IRQ0, MASK  
Software Interrupt Assertion  
Program code can generate interrupts directly. Writing a 1 to the correct bit in the Interrupt  
Request register triggers an interrupt (assuming that interrupt is enabled). When the inter-  
rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is  
automatically cleared to 0.  
The following coding style used to generate software interrupts by setting bits in the In-  
terrupt Request registers is NOT recommended. All incoming interrupts received be-  
tween execution of the first LDX command and the final LDX command are lost.  
Caution:  
Poor coding style that can result in lost interrupt requests:  
LDX r0, IRQ0  
OR r0, MASK  
LDX IRQ0, r0  
To avoid missing interrupts, use the following coding style to set bits in the Interrupt Re-  
quest registers:  
Caution:  
Good coding style that avoids lost interrupt requests:  
ORX IRQ0, MASK  
Interrupt Control Register Definitions  
For all interrupts other than the Watch-Dog Timer interrupt, the Primary Oscillator Fail  
Trap, and the Watchdog Oscillator Fail Trap, the interrupt control registers enable individ-  
ual interrupts, set interrupt priorities, and indicate interrupt requests.  
Interrupt Request 0 Register  
The Interrupt Request 0 (IRQ0) register (Table 32) stores the interrupt requests for both  
vectored and polled interrupts. When a request is presented to the interrupt controller, the  
corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vec-  
tored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If  
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt  
Request 0 register to determine if any interrupt requests are pending.  
PS024705-0405  
P R E L I M I N A R Y  
Interrupt Controller