Z8 Encore! XP® F08xA Series
Product Specification
47
Table 31. Trap and Interrupt Vectors in Order of Priority
Program Memory
Priority Vector Address
Highest 0002H
0004H
Interrupt or Trap Source
Reset (not an interrupt)
Watch-Dog Timer (see Watch-Dog Timer chapter)
Primary Oscillator Fail Trap (not an interrupt)
Watchdog Oscillator Fail Trap (not an interrupt)
Illegal Instruction Trap (not an interrupt)
Reserved
003AH
003CH
0006H
0008H
000AH
Timer 1
000CH
000EH
Timer 0
UART 0 receiver
0010H
UART 0 transmitter
0012H
Reserved
0014H
Reserved
0016H
ADC
0018H
Port A7, selectable rising or falling input edge
Port A6, selectable rising or falling input edge or Comparator Output
Port A5, selectable rising or falling input edge
Port A4, selectable rising or falling input edge
Port A3 or Port D3, selectable rising or falling input edge
Port A2 or Port D2, selectable rising or falling input edge
Port A1, selectable rising or falling input edge
Port A0, selectable rising or falling input edge
Reserved
001AH
001CH
001EH
0020H
0022H
0024H
0026H
0028H
002AH
Reserved
002CH
002EH
Reserved
Reserved
0030H
Port C3, both input edges
0032H
Port C2, both input edges
0034H
Port C1, both input edges
PS024705-0405
P R E L I M I N A R Y
Interrupt Controller
ZILOG [ ZILOG, INC. ]
