Z8 Encore! XP® F08xA Series
Product Specification
54
T1ENL—Timer 1 Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
IRQ1 Enable High and Low Bit Registers
Table 38 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit reg-
isters (Tables 39 and 40) form a priority encoded enabling for interrupts in the Interrupt
Request 1 register. Priority is generated by setting bits in each register.
Table 38. IRQ1 Enable and Priority Encoding
IRQ1ENH[x] IRQ1ENL[x] Priority
Description
Disabled
Low
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Nominal
High
where x indicates the register bits from 0–7.
Table 39. IRQ1 Enable High Bit Register (IRQ1ENH)
BITS
7
6
5
4
3
2
1
0
PA7ENH PA6CENH PA5ENH PA4ENH PA3ENH PA2ENH PA1ENH PA0ENH
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC4H
ADDR
PA6CENH—Port A Bit[6] or Comparator Interrupt Request Enable High Bit
PAxENH—Port A Bit[x] Interrupt Request Enable High Bit
Refer to the Shared Interrupt Select register for selection of either Port A or Port D as the
interrupt source.
PS024705-0405
P R E L I M I N A R Y
Interrupt Controller
ZILOG [ ZILOG, INC. ]
