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Z8F082ASH020SC 参数 Datasheet PDF下载

Z8F082ASH020SC图片预览
型号: Z8F082ASH020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采XP -R F08xA系列与扩展外设 [Z8 Encore XP-R F08xA Series with eXtended Peripherals]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 244 页 / 2750 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore! XP® F08xA Series  
Product Specification  
53  
IRQ0 Enable High and Low Bit Registers  
Table 35 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit reg-  
isters (Tables 36 and 37) form a priority encoded enabling for interrupts in the Interrupt  
Request 0 register. Priority is generated by setting bits in each register.  
Table 35. IRQ0 Enable and Priority Encoding  
IRQ0ENH[x] IRQ0ENL[x] Priority  
Description  
Disabled  
Low  
0
0
1
1
0
1
0
1
Disabled  
Level 1  
Level 2  
Level 3  
Nominal  
High  
where x indicates the register bits from 0–7.  
Table 36. IRQ0 Enable High Bit Register (IRQ0ENH)  
BITS  
7
6
5
4
3
2
1
0
Reserved  
T1ENH  
T0ENH  
U0RENH U0TENH Reserved Reserved ADCENH  
FIELD  
RESET  
R/W  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
FC1H  
ADDR  
Reserved—Must be 0.  
T1ENH—Timer 1 Interrupt Request Enable High Bit  
T0ENH—Timer 0 Interrupt Request Enable High Bit  
U0RENH—UART 0 Receive Interrupt Request Enable High Bit  
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit  
ADCENH—ADC Interrupt Request Enable High Bit  
Table 37. IRQ0 Enable Low Bit Register (IRQ0ENL)  
BITS  
7
6
5
4
3
2
1
0
Reserved  
T1ENL  
T0ENL  
U0RENL U0TENL Reserved Reserved ADCENL  
FIELD  
RESET  
R/W  
0
0
0
0
0
0
0
0
R
R/W  
R/W  
R/W  
R/W  
R
R
R/W  
FC2H  
ADDR  
Reserved—Must be 0.  
PS024705-0405  
P R E L I M I N A R Y  
Interrupt Controller