Z8 Encore! XP® F08xA Series
Product Specification
17
Table 7. Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
IRQ0ENL
IRQ1
Reset (Hex)
Page #
53
FC2
IRQ0 Enable Low Bit
Interrupt Request 1
IRQ1 Enable High Bit
IRQ1 Enable Low Bit
Interrupt Request 2
IRQ2 Enable High Bit
IRQ2 Enable Low Bit
Reserved
00
00
00
00
00
00
00
XX
00
00
00
FC3
52
FC4
IRQ1ENH
IRQ1ENL
IRQ2
54
FC5
55
FC6
52
FC7
IRQ2ENH
IRQ2ENL
—
55
FC8
56
FC9–FCC
FCD
FCE
FCF
Interrupt Edge Select
Shared Interrupt Select
Interrupt Control
IRQES
57
57
57
IRQSS
IRQCTL
GPIO Port A
FD0
Port A Address
Port A Control
PAADDR
PACTL
PAIN
00
00
XX
00
37
38
39
39
FD1
FD2
Port A Input Data
Port A Output Data
FD3
PAOUT
GPIO Port B
FD4
Port B Address
Port B Control
PBADDR
PBCTL
PBIN
00
00
XX
00
37
38
39
39
FD5
FD6
Port B Input Data
Port B Output Data
FD7
PBOUT
GPIO Port C
FD8
Port C Address
Port C Control
PCADDR
PCCTL
PCIN
00
00
XX
00
37
38
39
39
FD9
FDA
Port C Input Data
Port C Output Data
FDB
PCOUT
GPIO Port D
FDC
Port D Address
Port D Control
Reserved
PDADDR
PDCTL
—
00
00
XX
00
XX
37
38
FDD
FDE
FDF
Port D Output Data
Reserved
PDOUT
—
39
FE0–FEF
Watch-Dog Timer (WDT)
XX=Undefined
PS024705-0405
P R E L I M I N A R Y
Register Map
ZILOG [ ZILOG, INC. ]
