Z8 Encore! XP® F08xA Series
Product Specification
15
Register Map
Table 7 provides the address map for the Register File of the Z8 Encore! XP® F08xA
Series devices. Not all devices and package styles in the Z8 Encore! XP® F08xA Series
support the ADC, or all of the GPIO Ports. Consider registers for unimplemented periph-
erals as Reserved.
Table 7. Register File Address Map
Address (Hex) Register Description
General Purpose RAM
Mnemonic
Reset (Hex)
Page #
Z8F082A/Z8F081A Devices
000–3FF
400–EFF
General-Purpose Register File RAM
—
—
XX
XX
Reserved
Timer 0
F00
Timer 0 High Byte
T0H
00
01
FF
FF
00
00
00
00
72
72
73
73
73
74
74
75
F01
Timer 0 Low Byte
T0L
F02
Timer 0 Reload High Byte
Timer 0 Reload Low Byte
Timer 0 PWM High Byte
Timer 0 PWM Low Byte
Timer 0 Control 0
T0RH
F03
T0RL
F04
T0PWMH
T0PWML
T0CTL0
T0CTL1
F05
F06
F07
Timer 0 Control 1
Timer 1
F08
Timer 1 High Byte
T1H
00
01
FF
FF
00
00
00
00
XX
72
72
73
73
73
74
74
72
F09
Timer 1 Low Byte
T1L
F0A
Timer 1 Reload High Byte
Timer 1 Reload Low Byte
Timer 1 PWM High Byte
Timer 1 PWM Low Byte
Timer 1 Control 0
T1RH
T1RL
F0B
F0C
T1PWMH
T1PWML
T1CTL0
T1CTL1
—
F0D
F0E
F0F
Timer 1 Control 1
F10–F3F
Reserved
UART 0
F40
UART0 Transmit Data
UART0 Receive Data
U0TXD
U0RXD
XX
XX
95
96
XX=Undefined
PS024705-0405
P R E L I M I N A R Y
Register Map
ZILOG [ ZILOG, INC. ]
