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Z8F082ASH020SC 参数 Datasheet PDF下载

Z8F082ASH020SC图片预览
型号: Z8F082ASH020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采XP -R F08xA系列与扩展外设 [Z8 Encore XP-R F08xA Series with eXtended Peripherals]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 244 页 / 2750 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore! XP® F08xA Series  
Product Specification  
21  
Table 9. Reset Sources and Resulting Reset Type  
Operating Mode  
Reset Source  
Special Conditions  
NORMAL or HALT  
modes  
Power-On Reset / Voltage Brown- Reset delay begins after supply voltage  
Out  
exceeds POR level  
None  
Watch-Dog Timer time-out  
when configured for Reset  
RESET pin assertion  
All reset pulses less than three system clocks  
in width are ignored.  
On-Chip Debugger initiated Reset System Reset, except the On-Chip Debugger  
(OCDCTL[0] set to 1) is unaffected by the reset  
STOP mode  
Power-On Reset / Voltage Brown- Reset delay begins after supply voltage  
Out  
exceeds POR level  
RESET pin assertion  
All reset pulses less than the specified analog  
delay are ignored. See “Electrical  
Characteristics” on page 191.  
DBG pin driven Low  
None  
Power-On Reset  
Each device in the Z8 Encore! XP® F08xA Series contains an internal Power-On Reset  
(POR) circuit. The POR circuit monitors the supply voltage and holds the device in the  
Reset state until the supply voltage reaches a safe operating level. After the supply voltage  
exceeds the POR voltage threshold (VPOR), the device is held in the Reset state until the  
POR Counter has timed out. If the crystal oscillator is enabled by the option bits, this tim-  
eout is longer.  
After the ZZ8 Encore! XP® F08xA Series device exits the Power-On Reset state, the eZ8  
CPU fetches the Reset vector. Following Power-On Reset, the PORstatus bit in the Watch-  
Dog Timer Control (WDTCTL) register is set to 1.  
Figure 4 illustrates Power-On Reset operation. Refer to the “Electrical Characteristics” on  
page 191 for the POR threshold voltage (VPOR).  
PS024705-0405  
P R E L I M I N A R Y  
Reset and STOP Mode Recovery