Z8 Encore! XP® F08xA Series
Product Specification
20
Table 8. Reset and STOP Mode Recovery Characteristics and Latency (Continued)
Reset Characteristics and Latency
eZ8
Reset Type
Control Registers
CPU Reset Latency (Delay)
STOP Mode Recovery
Unaffected, except
WDT_CTL and
Reset 66 Internal Precision Oscillator Cycles
OSC_CTL registers
STOP Mode Recovery with Unaffected, except
Crystal Oscillator Enabled WDT_CTL and
OSC_CTL registers
Reset 5000 Internal Precision Oscillator Cycles
During a System Reset or STOP Mode Recovery, the Internal Precision Oscillator requires
4 µs to start up. Then, the Z8 Encore! XP® F08xA Series device is held in Reset for 66
cycles of the Internal Precision Oscillator. If the crystal oscillator is enabled in the Flash
option bits, this reset period is increased to 5000 IPO cycles. When a reset occurs because
of a low voltage condition or power on reset, this delay is measured from the time that the
supply voltage first exceeds the POR level (discussed later in this chapter). If the external
pin reset remains asserted at the end of the reset period, the device remains in reset until
the pin is deasserted.
At the beginning of Reset, all GPIO pins are configured as inputs with pull-up resistor dis-
abled, except PD0 which is shared with the reset pin. On reset, the Port D0 pin is config-
ured as a bidirectional open-drain reset. The pin is internally driven low during port reset,
after which the user code may reconfigure this pin as a general purpose output.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watch-Dog Timer oscillator continue to run.
Upon Reset, control registers within the Register File that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer, Regis-
ter Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8
CPU fetches the Reset vector at Program Memory addresses 0002Hand 0003Hand loads
that value into the Program Counter. Program execution begins at the Reset vector
address.
Because the control registers are re-initialized by a system reset, the system clock after
reset is always the IPO. User software must reconfigure the oscillator control block, such
that the correct system clock source is enabled and selected.
Reset Sources
Table 9 lists the possible sources of a system reset.
PS024705-0405
P R E L I M I N A R Y
Reset and STOP Mode Recovery
ZILOG [ ZILOG, INC. ]
