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Z8F012APB020SC 参数 Datasheet PDF下载

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型号: Z8F012APB020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采XP -R 4K系列高性能8位微控制器 [Z8 Encore XP-R 4K Series High-Performance 8-Bit Microcontrollers]
分类和应用: 微控制器外围集成电路光电二极管时钟
文件页数/大小: 276 页 / 3422 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore! XP® 4K Series  
Product Specification  
44  
drains if set to 1.  
0 = The source current is enabled for any output mode (unless overridden by the alternate  
function). (Push-pull output)  
1 = The source current for the associated pin is disabled (open-drain mode).  
Port A–D High Drive Enable Sub-Registers  
The Port A–D High Drive Enable sub-register (Table 23) is accessed through the Port  
A–D Control register by writing 04Hto the Port A–D Address register. Setting the bits in  
the Port A–D High Drive Enable sub-registers to 1 configures the specified port pins for  
high current output drive operation. The Port A–D High Drive Enable sub-register affects  
the pins directly and, as a result, alternate functions are also affected.  
Table 23. Port A–D High Drive Enable Sub-Registers (PxHDE)  
BITS  
7
6
5
4
3
2
1
0
PHDE7  
PHDE6  
PHDE5  
PHDE4  
PHDE3  
PHDE2  
PHDE1  
PHDE0  
FIELD  
RESET  
R/W  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
If 04H in Port A–D Address Register, accessible through the Port A–D Control Register  
ADDR  
PHDE[7:0]—Port High Drive Enabled  
0 = The Port pin is configured for standard output current drive.  
1 = The Port pin is configured for high output current drive.  
Port A–D STOP Mode Recovery Source Enable Sub-Registers  
The Port A–D STOP Mode Recovery Source Enable sub-register (Table 24) is accessed  
through the Port A–D Control register by writing 05Hto the Port A–D Address register.  
Setting the bits in the Port A–D STOP Mode Recovery Source Enable sub-registers to 1  
configures the specified Port pins as a STOP Mode Recovery source. During STOP Mode,  
any logic transition on a Port pin enabled as a STOP Mode Recovery source initiates  
STOP Mode Recovery.  
Table 24. Port A–D STOP Mode Recovery Source Enable Sub-Registers (PxSMRE)  
BITS  
7
6
5
4
3
2
1
0
PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMRE1 PSMRE0  
FIELD  
RESET  
R/W  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
If 05H in Port A–D Address Register, accessible through the Port A–D Control Register  
ADDR  
PSMRE[7:0]—Port STOP Mode Recovery Source Enabled  
0 = The Port pin is not configured as a STOP Mode Recovery source. Transitions on this  
PS022815-0206  
General-Purpose I/O