Z8 Encore! XP® 4K Series
Product Specification
41
Table 17. GPIO Port Registers and Sub-Registers (Continued)
Port Register Mnemonic
PxOC
Port Register Name
Output Control (Open-Drain)
High Drive Enable
PxHDE
PxSMRE
PxPUE
STOP Mode Recovery Source Enable
Pull-up Enable
PxAFS1
Alternate Function Set 1
Alternate Function Set 2
PxAFS2
Port A–D Address Registers
The Port A–D Address registers select the GPIO Port functionality accessible through the
Port A–D Control registers. The Port A–D Address and Control registers combine to pro-
vide access to all GPIO Port controls (Table 18).
Table 18. Port A–D GPIO Address Registers (PxADDR)
BITS
7
6
5
4
3
2
1
0
PADDR[7:0]
00H
FIELD
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FD0H, FD4H, FD8H, FDCH
ADDR
PADDR[7:0]—Port Address
The Port Address selects one of the sub-registers accessible through the Port Control reg-
ister.
PADDR[7:0] Port Control sub-register accessible using the Port A–D Control Registers
00H
01H
No function. Provides some protection against accidental Port reconfiguration.
Data Direction
02H
Alternate Function
03H
Output Control (Open-Drain)
High Drive Enable
04H
05H
STOP Mode Recovery Source Enable.
Pull-up Enable
06H
07H
Alternate Function Set 1
Alternate Function Set 2
No function
08H
09H–FFH
PS022815-0206
General-Purpose I/O
ZILOG [ ZILOG, INC. ]
