Z8 Encore! XP® 4K Series
Product Specification
42
Port A–D Control Registers
The Port A–D Control registers set the GPIO port operation. The value in the correspond-
ing Port A–D Address register determines which sub-register is read from or written to by
a Port A–D Control register transaction (Table 19).
Table 19. Port A–D Control Registers (PxCTL)
BITS
7
6
5
4
3
2
1
0
PCTL
00H
FIELD
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FD1H, FD5H, FD9H, FDDH
ADDR
PCTL[7:0]—Port Control
The Port Control register provides access to all sub-registers that configure the GPIO Port
operation.
Port A–D Data Direction Sub-Registers
The Port A–D Data Direction sub-register is accessed through the Port A–D Control regis-
ter by writing 01H to the Port A–D Address register (Table 20).
Table 20. Port A–D Data Direction Sub-Registers (PxDD)
BITS
7
6
5
4
3
2
1
0
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
FIELD
RESET
R/W
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 01H in Port A–D Address Register, accessible through the Port A–D Control Register
ADDR
DD[7:0]—Data Direction
These bits control the direction of the associated port pin. Port Alternate Function opera-
tion overrides the Data Direction register setting.
0 = Output. Data in the Port A–D Output Data register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A–D Input Data Reg-
ister. The output driver is tristated.
Port A–D Alternate Function Sub-Registers
The Port A–D Alternate Function sub-register (Table 21) is accessed through the Port A–
D Control register by writing 02Hto the Port A–D Address register. The Port A–D Alter-
nate Function sub-registers enable the alternate function selection on pins. If disabled, pins
PS022815-0206
General-Purpose I/O
ZILOG [ ZILOG, INC. ]
