Z8 Encore! XP® 4K Series
Product Specification
203
Table 127. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
r
src
Irr
Irr
r
C
Z
S
V
D
LDC dst, src
dst ← src
C2
C5
D2
C3
D3
–
–
–
–
–
–
2
2
2
2
2
5
9
5
9
9
Ir
Irr
Ir
LDCI dst, src
dst ← src
r ← r + 1
rr ← rr + 1
Irr
Ir
–
–
–
–
–
–
Irr
LDE dst, src
LDEI dst, src
dst ← src
r
Irr
r
82
92
83
93
–
–
–
–
–
–
–
–
–
–
–
–
2
2
2
2
5
5
9
9
Irr
Ir
dst ← src
r ← r + 1
rr ← rr + 1
Irr
Ir
Irr
LDWX dst, src
LDX dst, src
dst ← src
dst ← src
ER
r
ER
ER
ER
IRR
IRR
X(rr)
r
1FE8
84
85
86
87
88
89
94
95
96
97
E8
E9
98
99
F4
–
–
–
–
–
–
–
–
–
–
–
–
5
3
3
3
3
3
3
3
3
3
3
4
4
3
3
2
4
2
3
4
5
4
4
2
3
4
5
2
2
3
5
8
Ir
R
IR
r
X(rr)
ER
ER
IRR
IRR
ER
ER
r
r
Ir
R
IR
ER
IM
LEA dst, X(src)
MULT dst
dst ← src + X
X(r)
X(rr)
–
–
–
–
–
–
rr
dst[15:0] ←
dst[15:8] * dst[7:0]
RR
–
–
–
–
–
–
–
–
–
–
–
–
NOP
No operation
0F
1
2
Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS022815-0206
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
