Z8 Encore! XP® 4K Series
Product Specification
200
Table 127. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
r
src
r
C
Z
S
V
D
AND dst, src
dst ← dst AND src
52
53
54
55
56
57
58
59
2F
–
*
*
0
–
–
2
2
3
3
3
3
4
4
1
3
4
3
4
3
4
3
3
2
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
ANDX dst, src
ATM
dst ← dst AND src
–
–
*
*
0
–
–
–
–
–
Block all interrupt and
DMA requests during
execution of the next 3
instructions
–
–
BCLR bit, dst
BIT p, bit, dst
BRK
dst[bit] ← 0
r
r
E2
E2
00
E2
D5
F6
F7
F6
F7
F6
F7
D4
D6
–
–
–
–
X
–
*
*
*
*
0
0
–
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
1
2
2
3
3
3
3
3
3
2
3
2
2
1
2
2
3
4
3
4
3
4
6
3
dst[bit] ← p
Debugger Break
dst[bit] ← 1
–
*
–
*
BSET bit, dst
BSWAP dst
r
dst[7:0] ← dst[0:7]
R
*
*
BTJ p, bit, src, dst if src[bit] = p
PC ← PC + X
r
Ir
r
–
–
BTJNZ bit, src, dst if src[bit] = 1
PC ← PC + X
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Ir
r
BTJZ bit, src, dst if src[bit] = 0
PC ← PC + X
Ir
CALL dst
SP ← SP -2
@SP ← PC
PC ← dst
IRR
DA
CCF
C ← ~C
EF
B0
B1
*
–
–
–
–
–
–
–
–
–-
–
1
2
2
2
2
3
CLR dst
dst ← 00H
R
–
IR
Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS022815-0206
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
