Z8 Encore! XP® 4K Series
Product Specification
202
Table 127. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
Halt Mode
dst
src
C
–
–
Z
–
*
S
–
*
V
–
–
D
–
–
HALT
7F
20
–
–
1
2
2
1
2
2
1
2
2
3
2
5
6
5
INC dst
dst ← dst + 1
R
IR
21
r
0E-FE
A0
INCW dst
IRET
dst ← dst + 1
RR
IRR
–
*
*
*
*
*
*
*
–
*
–
*
A1
FLAGS ← @SP
SP ← SP + 1
PC ← @SP
BF
SP ← SP + 2
IRQCTL[7] ← 1
JP dst
PC ← dst
DA
IRR
DA
8D
C4
–
–
–
–
–
–
–
–
–
–
–
–
3
2
3
2
3
2
JP cc, dst
if cc is true
0D-FD
PC ← dst
JR dst
PC ← PC + X
DA
DA
8B
–
–
–
–
–
–
–
–
–
–
–
–
2
2
2
2
JR cc, dst
if cc is true
0B-FB
PC ← PC + X
LD dst, rc
dst ← src
r
r
IM
X(r)
r
0C-FC
C7
D7
E3
–
–
–
–
–
–
2
3
3
2
3
3
3
3
2
3
2
3
4
3
2
4
2
3
3
3
X(r)
r
Ir
R
R
E4
R
IR
IM
IM
r
E5
R
E6
IR
Ir
E7
F3
IR
R
F5
Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS022815-0206
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
