Z8 Encore! XP® 4K Series
Product Specification
201
Table 127. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
R
src
C
Z
S
V
D
COM dst
dst ← ~dst
60
61
–
*
*
0
–
–
2
2
2
2
3
3
3
3
3
3
4
4
4
4
5
5
4
4
2
2
2
2
2
2
1
2
2
3
3
4
3
4
3
4
3
4
3
4
3
4
3
3
3
3
2
3
2
3
5
6
2
3
IR
r
CP dst, src
dst - src
r
A2
*
*
*
*
–
–
r
Ir
A3
R
R
A4
R
IR
IM
IM
r
A5
R
A6
IR
r
A7
CPC dst, src
dst - src - C
1F A2
1F A3
1F A4
1F A5
1F A6
1F A7
1F A8
1F A9
A8
*
*
*
*
–
–
r
Ir
R
R
R
IR
IM
IM
ER
IM
ER
IM
R
IR
ER
ER
ER
ER
R
CPCX dst, src
CPX dst, src
DA dst
dst - src - C
dst - src
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
A9
dst ← DA(dst)
dst ← dst - 1
dst ← dst - 1
IRQCTL[7] ← 0
40
*
X
*
IR
R
41
DEC dst
30
–
–
IR
RR
IRR
31
DECW dst
80
*
81
DI
8F
–
–
–
–
–
–
–
–
–
–
–
–
DJNZ dst, RA
dst ← dst – 1
if dst ≠ 0
r
0A-FA
PC ← PC + X
EI
IRQCTL[7] ← 1
9F
–
–
–
–
–
–
1
2
Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS022815-0206
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
