Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
(Figures 33 and 34). After this point, the register cannot be
modified by any means, intentional or otherwise. The
WDTMR cannot be read and is located in Bank F of the Ex-
panded Register Group at address location 0FH.
1
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC System Clock
00
01
10
11
5 ms
10 ms
20 ms
80 ms
128 SCLK
256 SCLK
512 SCLK
2048 SCLK
*
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON
*
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
*
Reserved (Must be 0)
* Default setting after RESET
Figure 33. Watch-Dog Timer Mode Register
Write Only
DS97Z8X0500
P R E L I M I N A R Y
47
ZILOG [ ZILOG, INC. ]
