Z8018x Family
MPU User Manual
215
Table 38. Arithmetic and Logical Instructions (8-bit) (Continued)
Flags
Addressing
Immed Ext Ind Reg RegI Imp Rel Bytes States Operation
7
6
Z
4
2
1
0
Operation
Name
Mnemonics
Op Code
S
H
P/V
N
C
SUBC
SBC A,g
10 011 g
10 011 110
11 011 110
<m>
S
D
D
D
1
1
2
4
6
6
Ar-gr-c® Ar
•
•
•
•
•
•
•
•
•
V
V
V
S
S
S
•
•
•
SBC A,(HL)
SBC A,m
S
Ar-(HL) -c® Ar
M
S
Ar-m-c® Ar
SBC A,(IX + d) 11 011 101
S
S
D
D
3
3
14
14
Ar-(IX + d) -c® Ar
•
•
•
•
•
•
V
V
S
S
•
•
M
10 011 110
<d>
SBC A,(IY + d) 11 111 101
10 011 110
Ar-(IY + d) -c® Ar
M
<d>
TEST
TST g**
11 101 101
00 g 100
S
2
2
3
7
Ar·gr
•
•
•
•
•
•
S
S
S
P
P
P
R
R
R
R
R
R
TST {HL)**
00 110 100
TST m**
11101101
S
10
9
Ar·(HL)
M
11 101 101
01 100 100
<m>
S
Ar·m
XOR
XOR g
10 101 g
10 101 110
11 101 110
<m>
S
D
D
D
1
1
2
4
6
6
ArÅ + gr® Ar
•
•
•
•
•
•
R
R
R
P
P
P
R
R
R
R
R
R
XOR (HL)
XOR m
S
ArÅ + (HL) ® Ar
M
S
ArÅ + m® Ar
ArÅ + (IX + d)) ® Ar
XOR (IX + d)
11 011 101
10 101 110
<d>
S
D
3
14
•
•
R
P
R
R
M
UM005001-ZMP0400
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