Z8018x Family
MPU User Manual
102
Table 15. Channel 1 Transfer Mode
DIM1 DIM0 Transfer Mode
Address Increment/Decrement
0
0
1
1
0
1
0
1
Memory to I/O
Memory to I/O
I/O to Memory
I/O to Memory
MARI +1, IAR1 fixed
MARI -1, IAR1 fixed
IAR1 fixed, MAR1+1
IAR1 fixed, MAR1-1
DMA I/O Address Register Ch. 1 (IAR1B: 2DH) (Z8S180/L180-Class Processor Only)
Bit
7
6
5
4
Reserved
R/W
3
2
1
0
Bit/Field
R/W
R/W
0
R/W
0
R/W
0
R/W
0
Reset
0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W Value Description
7
R/W
Alternating Channels
DMA Channels are independent
Toggle between DMA channels for same device
Currently selected DMA channel when Bit 7 = 1
Reserved. Must be 0.
0
1
6
R/W
Reserved R/W
R/W
5–4
3
0
0
1
TOUT/DREQ is DREQ In
TOUT/DREQ is TOUT Out
UM005001-ZMP0400
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