eZ80L92 MCU
Product Specification
65
Table 20. Motorola Bus Mode Read States (Continued)
STATE S6 During state S6, data from the external peripheral device is driven onto the data bus.
STATE S7 On the rising edge of the clock entering state S7, the CPU latches data from the addressed
peripheral device and deasserts AS and DS. The peripheral device deasserts DTACK at
this time.
The eight states for a Write operation in Motorola Bus Mode are described in Table 21.
Table 21. Motorola Bus Mode Write States
STATE S0 The Write cycle starts in S0. The CPU drives R/W High (if a preceding Write cycle leaves R/
W Low).
STATE S1 Entering S1, the CPU drives a valid address on the address bus.
STATE S2 On the rising edge of S2, the CPU asserts AS and drives R/W Low.
STATE S3 During S3, the data bus is driven out of the high-impedance state as the data to be written is
placed on the bus.
STATE S4 At the rising edge of S4, the CPU asserts DS. The CPU waits for a cycle termination signal
DTACK (WAIT). If the termination signal is not asserted at least one full CPU clock period
prior to the rising clock edge at the end of S4, the CPU inserts WAIT (T
DTACK is asserted. Each WAIT state is a full bus mode cycle.
) states until
WAIT
STATE S5 During S5, no bus signals are altered.
STATE S6 During S6, no bus signals are altered.
STATE S7 Upon entering S7, the CPU deasserts AS and DS. As the clock rises at the end of S7, the
CPU drives R/W High. The peripheral device deasserts DTACK at this time.
PS013015-0316
Chip Selects and Wait States
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