eZ80L92 MCU
Product Specification
61
Intel® Bus Mode (Multiplexed Address and Data Bus)
During Read operations with multiplexed address and data, the Intel® Bus Mode employs
4 states (T1, T2, T3, and T4) as described in Table 18.
Table 18. Intel® Bus Mode Read States (Multiplexed Address and Data Bus)
STATE T1 The Read cycle begins in State T1. The CPU drives the address onto the
DATA bus and the associated Chip Select signal is asserted. The CPU
drives the ALE signal High at the beginning of T1. During the middle of T1,
the CPU drives ALE Low to facilitate the latching of the address.
STATE T2 During State T2, the CPU removes the address from the DATA bus and
asserts the RD signal. Depending upon the instruction, either the MREQ or
IORQ signal is asserted.
STATE T3 During State T3, no bus signals are altered. If the external ReadY (WAIT)
pin is driven Low at least one eZ80 system clock cycle prior to the
beginning of State T3, additional WAIT states (T
ReadY pin is driven High.
) are asserted until the
WAIT
STATE T4 The CPU latches the Read data at the beginning of State T4. The CPU de-
®
asserts the RD signal and completes the Intel Bus Mode cycle.
During Write operations with multiplexed address and data, the Intel® Bus Mode employs
4 states (T1, T2, T3, and T4) as described in Table 19.
Table 19. Intel® Bus Mode Write States (Multiplexed Address and Data Bus)
STATE T1 The Write cycle begins in State T1. The CPU drives the address onto the
DATA bus and drives the ALE signal High at the beginning of T1. During
the middle of T1, the CPU drives ALE Low to facilitate the latching of the
address.
STATE T2 During State T2, the CPU removes the address from the DATA bus and
drives the Write data onto the DATA bus. The WR signal is asserted to
indicate a Write operation.
STATE T3 During State T3, no bus signals are altered. If the external ReadY (WAIT)
pin is driven Low at least one eZ80 system clock cycle prior to the
beginning of State T3, additional WAIT states (T
ReadY pin is driven High.
) are asserted until the
WAIT
STATE T4 The CPU deasserts the Write signal at the beginning of T4 identifying the
end of the Write operation. The CPU holds the data and address buses
through the end of T4. The bus cycle is completed at the end of T4.
PS013015-0316
Chip Selects and Wait States
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